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MGSF2P02HD Product Preview Power MOSFET 2 Amps, 20 Volts
P-Channel TSOP-6
This device represents a series of Power MOSFETs which are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature TSOP-6 Surface Mount Package - Saves Board Space * Low Profile for Thin Applications such as PCMCIA Cards * Very Low RDS(on) Provides Higher Efficiency and Expands Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode is Characterized for Use in Bridge Circuits * Diode Exhibits High Speed, with Soft Recovery * IDSS Specified at Elevated Temperatures * Avalanche Energy Specified * Package Mounting Information Provided
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2 AMPERES 20 VOLTS RDS(on) = 175 mW
P-Channel 1256
3
4
MARKING DIAGRAM
3 2
1
4
TSOP-6 CASE 318G STYLE 1
3V W
5
6
W
= Work Week
PIN ASSIGNMENT
Drain Drain Source
6 5 4
1
2
3
Drain Drain Gate
ORDERING INFORMATION
Device MGSF2P02HDT1 MGSF2P02HDT3
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
Package TSOP-6 TSOP-6
Shipping 3000 Tape & Reel 10,000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2000
1
November, 2000 - Rev. 1
Publication Order Number: MGSF2P02HD/D
MGSF2P02HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage Drain Current - Continuous Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance - Junction to Ambient (Note 1.) Drain Current - Continuous Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance - Junction to Ambient (Note 2.) Operating and Storage Temperature Range Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk, IL = 3.6 Apk, L = 25 mH, RG = 25 W Symbol VDSS VDGR VGS ID IDM PD PD RqJA ID IDM PD PD RqJA TJ, Tstg EAS 160 C Value 20 20 9 1.3 10 400 210 312 2.9 15 2.0 1.0 62.5 - 55 to 150 Unit V V V A mW mW C/W A W W C/W C mJ
THERMAL CHARACTERISTICS
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds TL 1. Minimum FR-4 or G-10 PCB, Operating to Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Operating time 5 seconds. 260
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-to-Source Leakage Current (VGS = 9.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) Drain-to-Source On-Voltage (VGS = 4.5 Vdc, ID = 1.3 Adc) (VGS = 2.7 Vdc, ID = 0.8 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.6 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 0.6 Adc, VGS = 2.7 Vdc, 2 7 Vdc RG = 6.0 ) (VDS = 10 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc, 4 5 Vdc RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.2 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 1.2 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) trr ta tb QRR NOTE: Pulse Test: Pulse Width 300 s, Duty Cycle 2%. VSD - - - - - - 0.89 0.72 86 27 59 0.115 1.1 - - - - - C nsec Vdc - - - - - - - - - - - - 15 27 60 72 20 94 49 76 5.3 0.7 2.6 1.9 - - - - - - - - 7.5 - - - nC nsec (VDS = 15 Vd VGS = 0 Vdc, Vdc, Vd f = 1.0 MHz) Ciss Coss Crss - - - 225 150 60 - - - pF VGS(th) 0.7 - RDS(on) - - gFS 1.3 2.0 - 145 220 175 280 mhos 0.95 2.2 1.4 - Vdc mV/C mW V(BR)DSS 20 IDSS - - IGSS - - - - 1.0 10 nAdc 100 - - A Vdc Symbol Min Typ Max Unit
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TYPICAL ELECTRICAL CHARACTERISTICS
4.0 4.0 2.9 V ID , DRAIN CURRENT (AMPS) TJ = 25C
VGS = 8.0 V 4.5 V 3.7 V 3.3 V
3.1 V
VDS 10 V
ID , DRAIN CURRENT (AMPS)
3.0
2.7 V 2.5 V 2.3 V 2.1 V 1.9 V 1.7 V
3.0
2.0
2.0
1.0
1.0
100C
25C TJ = -55C
0
0
0.4 0.8 1.2 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
2.0
0
0
1.0
2.0
3.0
4.0
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.4 0.6 0.5 0.4 0.3 0.2 0.1 0
Figure 2. Transfer Characteristics
TJ = 25C
0.3
ID = 1.3 A TJ = 25C
0.2
VGS = 2.7 V
0.1
4.5 V
0
0
2.0
4.0
6.0
8.0
10
0
1.0
2.0 ID, DRAIN CURRENT (AMPS)
3.0
4.0
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 3. On-Resistance versus Drain Current
Figure 4. On-Resistance versus Drain Current and Gate Voltage
100
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.0 VGS = 4.5 V ID = 0.8 A IDSS , LEAKAGE (nA) 1.5
TJ = 125C 10 100C
1.0
1.0 25C 0.1 VGS = 0 V 0 4.0 8.0 12 16 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.5
0
-50
- 25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 5. On-Resistance versus Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
800 Ciss C, CAPACITANCE (pF) 600 VDS = 0 V VGS = 0 V
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
Crss
400 Ciss Coss Crss 0 -10 VGS 0 VDS 10 20
200
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MGSF2P02HD
VGS, GATE TO SOURCE VOLTAGE (VOLTS) 5.0 QT 4.0 3.0 Q1 2.0 1.0 Q3 0 0 1.0 2.0 3.0 4.0 5.0 0 6.0 ID = 1.2 A TJ = 25C Q2 VDS VGS 16 12 VDS , DRAIN TO SOURCE VOLTAGE (VOLTS) 20 1000 VDD = 10 V ID = 1.2 A VGS = 4.5 V TJ = 25C
t, TIME (ns)
100
8.0 4.0
tf td(off) tr
10
td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2.0 IS, SOURCE CURRENT (AMPS) 1.6 1.2 0.8 VGS = 0 V TJ = 25C I S , SOURCE CURRENT
high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
di/dt = 300 A/s
Standard Cell Density trr High Cell Density trr tb ta
0.4 0
0.4
0.5
0.6
0.7
0.8
0.9
1.0 t, TIME
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current http://onsemi.com
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Figure 11. Reverse Recovery Time (trr)
MGSF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 0.5 TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.0001 0.001 0.01 0.1 t, TIME (s) P(pk) t1 t2 DUTY CYCLE, D = t1/t2 1.0 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 RJC(t) = r(t) RJC TJ(pk) - TC = P(pk) RJC(t) 10 100
Figure 12. Thermal Response
di/dt IS trr ta tp IS tb TIME 0.25 IS
Figure 13. Diode Reverse Recovery Waveform
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MGSF2P02HD INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm
TSOP-6 POWER DISSIPATION The power dissipation of the TSOP-6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP-6 package, PD can be calculated as follows:
PD = TJ(max) - TA RJA
one can calculate the power dissipation of the device which in this case is 400 milliwatts.
PD = 150C - 25C 312C/W = 400 milliwatts
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,
The 312C/W for the TSOP-6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 400 milliwatts. There are other alternatives to achieving higher power dissipation from the TSOP-6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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MGSF2P02HD
PACKAGE DIMENSIONS
TSOP-6 CASE 318G-02 ISSUE G
A L
6 5 1 2 4 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 DRAIN DRAIN GATE SOURCE DRAIN DRAIN INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181
S
B
D G M 0.05 (0.002) H C K J
STYLE 1: PIN 1. 2. 3. 4. 5. 6.
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MGSF2P02HD
Notes
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Notes
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MGSF2P02HD
Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MGSF2P02HD/D

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